? semiconductor components industries, llc, 2002 april, 2002 rev. 1 1 publication order number: an1686/d an1686/d intelligent ldo regulator with external bypass control prepared by: lonne mays introduction glitch-free supply transition from the 5 v primary supply to the auxiliary 3.3 v supply can be easily implemented for pci/nic and other motherboard slot cards via the mc33565 intelligent ldo regulator. this linear regulator contains detection and logic circuitry to determine which supply is active and take appropriate action to maintain a steady 3.3 v output, even as the supply planes change from aworkingo state to asystem sleepo state. the advanced configuration and power interface (acpi) design specification for managing power consumption within pc's provides for various power consumption states from g0 (cpu actively executing code) to four different levels (s1-s4) within the g1 sleep state. the system can be roused from the various levels of the sleep state without requiring a reboot of the operating system because both the system hardware and software save large elements of the system context. to be acpi compliant, network cards and modems plugged into the motherboard should be designed to function both from the 5 v main supply plane (available in g0 state) and the auxiliary 3.3 v supply (available in g1 state). acpi compliant systems can provide important benefits to the end-user, including: ? pc's appear aoffo and quiet when not actively in use, but resume full operation when required. ? network communication can be received by an acpi compliant card even though the pc is in sleep state. ? energy efficient operation without inconveniencing the end-user. 1 the mc33565 intelligent ldo has been developed to provide the hardware designer a convenient and easy implementation of the dual supply compliance. an external bypass mosfet is controlled by the mc33565 to connect the 3.3 v auxiliary supply directly to the output, thus bypassing the internal linear low dropout regulator whenever the 5 v main supply is not present. when the 5 v main supply power is present, the internal ldo circuitry regulates this down to 3.3 v and provides it to the output at currents up to 200 ma (the bypass mosfet's gate is biased aoffo at this time). the internal 5 v detection and logic circuitry has sufficient hysteresis to prevent inappropriate toggling between the two supplies if a full load is suddenly applied. (note: this requires that the source impedance of the 5 v supply, including wiring and printed circuit trace dcr, be less than 0.25 ohm for 200 ma loads.) power dissipation of the mc33565, when mounted appropriately on conventional fr4 epoxy pcb, is suf ficient to support regulation of the 5 v input down to 3.3 v at an output current of 200 ma. the power dissipated by the external bypass p-channel mosfet is a function of its r ds(on) . the dissipation is trivial with the recommended MGSF1P02ELt1 sot-23 packaged mosfet which has a typical r ds(on) of 400 milliohms at v gs = 2.5 v. p-channel mosfets with similar or lower r ds(on) and gate sensitivity parameters should work as well. functional description the mc33565 device contains 121 active transistors comprising the following functions: ? low dropout regulator ? internal voltage reference and 5 v detection circuitry ? voltage compensation and hysteresis control ? voltage comparator and mosfet gate driver figure 1 depicts the functional relationships in block diagram form. note that the 3.3 v in is an input to both the mc33565 and to the drain of the external p-channel mosfet. the 3.3 v out is derived either internally via linear regulation from the +5 v in input, or else is simply passed directly from the +3.3 v in input to the +3.3 v out via statically gating on the external mosfet which then acts as a bypass switch around the ldo. http://onsemi.com application note
an1686/d http://onsemi.com 2 figure 1. v ref compensation & hysteresis +5 v in ref & detect 5v detect comp driver drive out +3.3 v out sense in +3.3 v in hyst sw external p-channel mosfet +3.3 v out external 4.7 m f cap ldo the voltage reference and 5 v detection circuitry provides the reference for ldo regulation and also provides a 5 v detect signal which acts as a disable to the mosfet driver circuitry. the +3.3 v out , therefore, is provided via regulation down from the +5 v in whenever +5 v in is present. when +5 v in is absent, the mosfet driver is enabled and the external mosfet can pass the +3.3 v supply directly to the output. by using an appropriately low r ds(on) rated p-channel mosfet, trivial voltage will be dropped across the drain-source impedance of the transistor. compensation and hysteresis circuitry is provided to prevent the overall circuit from oscillating (bouncing or toggling) between enabling the mosfet and enabling the ldo when making the transition when significant load is present. the hysteresis provided is sufficient to permit glitch-free transitions with +5 v in source impedances as high as 250 milliohms (at 200 ma loading). as long as the source impedance, including cabling and pcb trace dcr, is less than 250 milliohms, we are assured that i o x r source < v hyst , thus avoiding mosfet drive bounce during the 5 v detect threshold transitions. the diagram below illustrates a minimum configuration for utilizing the mc33565. the only external components required are a p-channel mosfet such as the sot-23 packaged MGSF1P02ELt and a capacitor of at least 4.7 m f with maximum esr of 500 milliohms. (note 22 m f is recommended to ensure stable operation over the temperature range, as the temperature coefficients of many capacitor types are both large and poorly controlled.) figure 2. motherboard/ mainboard pci/nic slot +5 v in n/c +3.3 v in gnd drive out +3.3 v out sense in n/c 1 2 3 4 8 7 6 5 mc33565 pci/nic card circuitry 5v 3.3v aux 4.7 m f
an1686/d http://onsemi.com 3 reference design example a more conservative design approach would include additional filter capacitors on both the input and output. for example, to allow for varying distances from the supply planes' bulk filter capacitance, the designer could incorporate 4.7 m f tantalum or ceramic and 0.1 m f ceramic capacitors close to the +5 v in input pin. this combination would provide robustness to input voltage droop (during rapid changes in load) as well as provide high frequency decoupling. high frequency decoupling capacitors would also be recommended close to the +3.3 v in and +3.3 v out pins. the pcb copper and component layout artwork and schematic below (figures 3, 4, and 5) incorporate the above recommendations. also included is provision for either jumpering the sense input directly to the +3.3 v out , or connecting it to the load via an external non-current-carrying trace. figure 3. pcb component layout +5 vin from mother board (e.g., pci slot) d regulator bypass mosfet sense 3 1 4 8 7 6 mc33565 intelligent ldo 3.3 v aux 4.7 m f c4 0.1 m f c5 0.1 m f c1 0.1 m f c3 4.7 m f c2 s g to 3.3 v circuitry (network card/ modem / etc.) 3.3 v out figure 4. pcb copper layout figure 5. pcb schematic by using the artwork in figures 3 and 4 to create a small surface mount single sided evaluation board (components and copper on the same side), the reference design can be easily breadboarded onto existing prototype pci (or other form factor) cards. summary the mc33565 has been designed to provide easy implementation of acpi power management for pci and network interface cards (nics), where operation from a 3.3 v auxiliary supply is required when the 5 v supply has been shut down due to the main processor entering a reduced power state (e.g., sleep state). the mc33565 permits glitch-free transitions from asleepo to aactiveo system modes by providing the internal logic circuitry to detect whether the system is being powered from the motherboard main 5 v power supply or the 3.3 v aux supply. the mc33565 provides a regulated output voltage of 3.3 v via either an internal low dropout 5.0 v-to-3.3 v voltage regulator or an external p-channel mosfet, depending on the operating status of the system. during normal operating mode (5 v main supply available), the 3.3 v output is provided from the internal low dropout regulator at an output current of 200 ma. when the motherboard enters sleep mode, the mc33565 operates from the 3.3 v aux supply and routes the aux current to the
an1686/d http://onsemi.com 4 output via the external p-channel mosfet bypass transistor. as a result, the output voltage provided to the peripheral card remains constant at 3.3 v even during transitions to and from sleep mode. references 1. mobile power guidelines 2000 , pp51, rev 1.0, dec. 11, 1998, intel corporation. 2. pci bus power management: hardware considerations for pci 3.3 vaux implementations , wireless symposium / portable by design, san jose ca, 1999. 3. abasic semiconductor thermal measuremento, gary e. dashney, thermal modeling and management of discrete surface mount packages , on semiconductor document br1487/d rev 1. 4. athermal characterization of the so-8 package for power semiconductor applications,o kent kime, mike lissy, dave shumate, larry walker, thermal modeling and management of discrete surface mount packages , on semiconductor document br1487/d rev 1. on semiconductor is a trademark and is a registered trademark of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may b e provided in scillc data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. an1686/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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